Datasheet

DM7490A Decade and Binary Counters

August 1986 Revised March 2000

DM7490A Decade and Binary Counters
General Description
The DM7490A monolithic counter contains four masterslave flip-flops and additional gating to provide a divide-bytwo counter and a three-stage binary counter for which the count cycle length is divide-by-five. The counter has a gated zero reset and also has gated setto-nine inputs for use in BCD nine’s complement applications. To use the maximum count length (decade or four-bit binary), the B input is connected to the QA output. The input count pulses are applied to input A and the outputs are as described in the appropriate Function Table. A symmetrical divide-by-ten count can be obtained from the counters by connecting the QD output to the A input and applying the input count to the B input which gives a divideby-ten square wave at output QA.

Features s Typical power dissipation 145 mW s Count frequency 42 MHz

Ordering Code:
Order Number DM7490AN Package Number N14A Package Description 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

Connection Diagram

© 2000 Fairchild Semiconductor Corporation

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DM7490A

Function Tables
BCD Count Sequence (Note 1) Count QD 0 1 2 3 4 5 6 7 8 9 L L L L L L L L H H L L L L H H H H L L Outputs QC QB L L H H L L H H L L QA L H L H L H L H L H

Logic Diagram

BCD Bi-Quinary (5-2) (Note 2) Count QA 0 1 2 3 4 5 6 7 8 9 L L L L L H H H H H L L L L H L L L L H Outputs QD QC L L H H L L L H H L QB L H L H L L H L H L

Reset/Count Function Table Reset Inputs R0(1) H H X X L L X
H = HIGH Level L = LOW Level X = Don’t Care Note 1: Output QA is connected to input B for BCD count. Note 2: Output QD is connected to input A for bi-quinary count

Outputs R9(2) X L H L X L X QD L L H QC L L L QB L L L QA L L H

R0(2) H H X L X X L

R9(1) L X H X L X L

The J and K inputs shown without connection are for reference only and are