Udson

XXII Conference on Design of Circuits and Integrated Systems

ISBN-13 978-84690-8629-2

VOLTAGE FLUCTUATIONS IN IC POWER SUPPLY DISTRIBUTION NETWORKS: IMPACT ON DIGITAL PROCESSING SYSTEMS
Dennis Andrade, Ferran Martorell, Francesc Moll, Antonio Rubio Technical University of Catalonia (UPC) Barcelona, Spain [e-mail]
Abstract— The supply voltage decrease and power consumption increase of modern ICs made the requirements for low voltage fluctuation caused by packaging and on-chip parasitic impedances more difficult to achieve. Most of the research works on the area assume that all the nodes of the chip are fed at the same voltage, in such a way that the main cause of disturbance or fluctuation is the parasitic impedance of packaging. In the paper an approach to analyze the effect of high and fast current demands on the on-chip power supply network. First an approach to model the entire network by considering a homogeneous conductive foil is presented. The modification of the timing parameters of flipflops caused by spatial voltage drops through the IC surface are also investigated. Index Terms— CMOS, integrated circuits ground bounce, power supply voltage fluctuations, noise, digital circuit performances.

the impact and cost of ground bounce and power supply fluctuations is one of the most active topics currently addressed by researchers [1, 2]. Typically, in many of these research works the mechanism of the voltage fluctuations is modeled by the use of a lumped and uni-dimensional serial electric circuit as shown in Fig. 1, taken from [3]. The VDD power supply package pins are modeled by an inductance and a serial resistance together with a parasitic capacitance, all lumped components. Later, the power lines are applied to the digital cells with the consideration of a parasitic resistance for the distribution network and a capacitor resulting from the parasitic and on-chip decoupling capacitances. This model explains in a first approach the two