Melissasimoes

Using ModelSim to Simulate Logic Circuits in VHDL Designs
For Quartus II 12.1

1 Introduction
This tutorial is a basic introduction to ModelSim, a Mentor Graphics simulation tool for logic circuits. We show how to perform functional and timing simulations of logic circuits implemented by using Quartus II CAD software. The reader is expected to have the basic knowledge of VHDL, and the Altera Quartus® II CAD software. Contents: • Introduction to simulation • What is ModelSim? • Functional simulation using ModelSim • Timing simulation using ModelSim

Altera Corporation - University Program October 2012

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U SING M ODEL S IM TO S IMULATE L OGIC C IRCUITS IN VHDL D ESIGNS

For Quartus II 12.1

2 Background
Designers of digital systems are inevitably faced with the task of testing their designs. Each design can be composed of many components, each of which has to be tested in isolation and then integrated into a design when it operates correctly. To verify that a design operates correctly we use simulation, which is a process of testing the design by applying inputs to a circuit and observing its behavior. The output of a simulation is a set of waveforms that show how a circuit behaves based on a given sequence of inputs. The general flow of a simulation is shown in Figure 1. There are two main types of simulation: functional and timing simulation. The functional simulation tests the logical operation of a circuit without accounting for delays in the circuit. Signals are propagated through the circuit using logic and wiring delays of zero. This simulation is fast and useful for checking the fundamental correctness of the designed circuit. The second step of the simulation process is the timing simulation. It is a more complex type of simulation, where logic components and wires take some time to respond to input stimuli. In addition to testing the logical operation of the circuit, it shows the timing of signals in the circuit. This type of simulation is