Senhor

Inter Integrated Circuits bus by Philips Semiconductors

I2C bus
Tomáš Matoušek tmd.havit.cz

Basic Characteristics
• • • two-wired bus originally to interact within small num. of devs (radio/TV tuning, …) speeds:
– 100 kbps (standard mode) – 400 kbps (fast mode) – 3.4 Mbps (high-speed mode)

• • • • •

data transfers: serial, 8-bit oriented, bi-directional master/slave relationships with multi-master option (arbitration) master can operate as transmitter or receiver addressing: 7bit or 10bit unique addresses device count limit: max. capacitance 400 pF

Standard Mode

Wires and Signals
• two-wired bus
– serial data line (SDA) – serial clock line (SCL)

• voltage levels
– HIGH 1 – LOW 0 – not fixed, depends on associated level of voltage

• bit transfer (level triggered)
– – – – SCL = 1 ⇒ SDA = valid data one clock pulse per data bit stable data during high clocks data change during low clocks

Wired-AND connection
• bus is free ⇒ SDA and SCL are high
– by pull-up resistors

• device output is ANDed with signal on bus

Frame
• start condition (S) – SDA 1→0 transition when SCL = 1 • stop condition (P) – SDA 0→1 transition when SCL = 1 • repeated start (Sr)
– start is generated instead of stop

• bus state
– busy … after S and before next P – free … after P and before next S

Masters and Slaves
• Master device
– controls the SCL – starts and stops data transfer – controls addressing of other devices

• Slave device
– device addressed by master

• Transmitter/Receiver
– master or slave – master-transmitter sends data to slave-recevier – master-receiver requires data from slave-transmitter

Data Transfer
• • • • • data bits are transferred after start condition transmission is byte oriented byte = 8 bits + one acknowledge bit most significant bit (MSB) first slave address is also datum
– first byte transferred – during the first byte transfer:
• master is transmitter • addressed slave is receiver

– next bytes: